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low noise, precision instrumentation amplifier data sheet amp01 rev. e document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?1999C2017 analog devices, inc. all rights reserved. technical support www.analog.com features low offset voltage: 50 v maximum very low offset voltage drift: 0.3 v/ c maximum low noise: 0.12 v p-p (0.1 hz to 10 hz) excellent output drive: 10 v at 50 ma capacitive load stability: up to 1 f gain range: 0.1 to 10,000 excellent linearity: 16-bit at g = 1000 high cmr: 125 db minimum (g = 1000) low bias current: 4 na maximum can be configured as a precision op amp output-stage thermal shutdown available in die form general description the amp01 1 is a monolithic instrumentation amplifier designed for high-precision data acquisition and instrumen- tation applications. the design combines the conventional features of an instrumentation amplifier with a high current output stage. the output remains stable with high capacitance loads (1 f), a unique ability for an instrumentation amplifier. consequently, the amp01 can amplify low level signals for transmission through long cables without requiring an output buffer. the output stage can be configured as a voltage or current generator. input offset voltage is very low (20 v), which generally eliminates the external null potentiometer. temperature changes have minimal effect on offset; tcv ios is typically 0.15 v/c. excellent low frequency noise performance is achieved with a minimal compromise on input protection. the bias current is very low, less than 10 na over the military tempe rature range. high common-mode rejection of 130 db, 16-bit linearity at a gain of 1000, and 50 ma peak output current are achievable simultaneously. this combination takes the instrumentation amplifier one step further towards the ideal amplifier. ac performance complements the superb dc specifications. the amp01 slews at 4.5 v/s into capacitive loads of up to 15 nf, settles in 50 s to 0.01% at a gain of 1000, and boasts a healthy 26 mhz gain bandwidth product. these features make the amp01 ideal for high speed data acquisition systems. the gain is set by the ratio of two external resistors over a range of 0.1 to 10,000. a very low gain temperature coefficient of 10 ppm/c is achievable over the whole gain range. output voltage swing is guaranteed with three load resistances: 50 , 500 , and 2 k. loaded with 500 , the output delivers 13.0 v minimum. a thermal shutdown circuit prevents destruction of the output transistors during overload conditions. the amp01 can also be configured as a high performance operational amplifier. in many applications, the amp01 can be used in place of op amp/power buffer combinations. functional block diagram v ios null r g r s v oos null r1 47.5k ? r2 2.5k ? r4 2.5k ? r3 47.5k ? a1 a3 a2 q1 q2 250 ? 250 ? ?in +in reference v + +v op output ?v op sense v? 14335-004 figure 1. 1 protected under u.s. patents 4,471,321 and 4,503,381.
amp01* product page quick links last content update: 01/16/2017 comparable parts view a parametric search of comparable parts documentation application notes ? an-244: a user's guide to i.c. instrumentation amplifiers ? an-245: instrumentation amplifiers solve unusual design problems ? an-282: fundamentals of sampled data systems ? an-589: ways to optimize the performance of a difference amplifier ? an-671: reducing rfi rectification errors in in-amp circuits data sheet ? amp01: low noise, precision instrumentation amplifier data sheet ? amp01: military data sheet technical books ? a designer's guide to instrumentation amplifiers, 3rd edition, 2006 tools and simulations ? in-amp error calculator ? amp01 spice macro-model reference materials technical articles ? auto-zero amplifiers ? high-performance adder uses instrumentation amplifiers ? input filter prevents instrumentation-amp rf-rectification errors ? the ad8221 - setting a new industry standard for instrumentation amplifiers design resources ? amp01 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all amp01 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number *this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
amp01 data sheet rev. e | page 2 of 29 table of contents features .............................................................................................. 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? electrical characteristics ............................................................. 3 ? dice characteristics ..................................................................... 8 ? wafer test limits (amp01nbc) ............................................... 9 ? absolute maximum ratings .......................................................... 10 ? thermal resistance .................................................................... 10 ? esd caution ................................................................................ 10 ? pin configurations and function descriptions ......................... 11 ? typical performance characteristics ........................................... 13 ? theory of operation ...................................................................... 18 ? input and output offset voltages ............................................ 18 ? input bias and offset currents ................................................. 18 ? gain .............................................................................................. 18 ? common-mode rejection ........................................................ 19 ? active guard drive .................................................................... 19 ? grounding ................................................................................... 19 ? sense and reference terminals ................................................ 20 ? driving 50 loads .................................................................... 21 ? heatsinking ................................................................................. 22 ? overvoltage protection .............................................................. 22 ? power supply considerations ................................................... 22 ? applications circuits ...................................................................... 23 ? outline dimensions ....................................................................... 29 ? ordering guide .......................................................................... 29 revision history 1/2017rev. d to rev. e updated format .................................................................. universal deleted e-28a package ...................................................... universal changed r-20 package to rw-20 package ...................... universal deleted pin connections section and figure 1 to figure 3; renumbered sequentially ................................................................ 1 added functional block diagram section and figure 1; renumbered sequentially ................................................................ 1 changes to figure 2 .......................................................................... 8 changes to table 5 ............................................................................ 9 deleted figure 5 ................................................................................ 9 deleted table 6; renumbered sequentially ................................ 10 added table 6 and table 7; renumbered sequentially ............. 10 added pin configurations and function descriptions section, figure 3, and table 8 ...................................................................... 11 added figure 4 and table 9 .......................................................... 12 changes to input and output offset voltages section and gain section .................................................................................... 18 changes to power supply considerations section .................... 22 added applications circuits section ........................................... 29 updated package drawings .......................................................... 29 changes to ordering guide .......................................................... 29 12/1999revision 0: initial version
data sheet amp01 rev. e | page 3 of 29 specifications electrical characteristics v s = 15 v, r s = 10 k, r l = 2 k, t a = 25c, unless otherwise noted. table 1. test conditions/comments amp01a amp01b parameter symbol min typ max min typ max unit offset voltage input offset voltage v ios t a = 25c 20 50 40 100 v ?55c t a +125c 40 80 60 150 v input offset voltage drift tcv ios ?55c t a +125c 0.15 0.3 0.3 1.0 vc output offset voltage v oos t a = 25c 1 3 2 6 mv ?55c t a +125c 3 6 6 10 mv output offset voltage drift tcv oos r g = ?55c t a +125c 20 50 50 120 v/c offset referred to input vs. positive supply psr v+ = +5 v to +15 v g = 1000 120 130 110 120 db g = 100 110 130 100 120 db g = 10 95 110 90 100 db g = 1 75 90 70 80 db ?55c t a +125c g = 1000 120 130 110 120 db g = 100 110 130 100 120 db g = 10 95 110 90 100 db g = 1 75 90 70 80 db offset referred to input vs. negative supply psr v? = ?5 v to ?15 v g = 1000 105 125 105 115 db g = 100 90 105 90 95 db g = 10 70 85 70 75 db g = 1 50 65 50 60 db ?55c t a +125c g = 1000 105 125 105 115 db g = 100 90 105 90 95 db g = 10 70 85 70 75 db g = 1 50 85 50 60 db input offset voltage trim range v s = 4.5 v to 18 v 1 6 6 mv output offset voltage trim range v s = 4.5 v to 18 v 1 100 100 mv input current input bias current i b t a = 25c 1 4 2 6 na ?55c t a +125c 4 10 6 15 na input bias current drift tci b ?55c t a +125c 40 50 pa/c input offset current i os t a = 25c 0.2 1.0 0.5 2.0 na ?55c t a +125c 0.5 3.0 1.0 6.0 na input offset current drift tci os ?55c t a +125c 3 5 pa/c
amp01 data sheet rev. e | page 4 of 29 test conditions/comments amp01a amp01b parameter symbol min typ max min typ max unit input input resistance r in differential, g = 1000 1 1 g differential, g 100 10 10 g common mode, g = 1000 20 20 g input voltage range ivr t a = 25c 2 10.5 10.5 v ?55c t a +125c 10.0 10.0 v common-mode rejection cmr v cm = 10 v, 1 k source imbalance g = 1000 125 130 115 125 db g = 100 120 130 110 125 db g = 10 100 120 95 110 db g = 1 85 100 75 90 db ?55c t a +125c g = 1000 120 125 110 120 db g = 100 115 125 105 120 db g = 10 95 115 90 105 db g = 1 80 95 75 90 db 1 v ios and v oos nulling have minimal affect on tcv ios and tcv oos , respectively. 2 refer to the common-mode rejection section.
data sheet amp01 rev. e | page 5 of 29 v s = 15 v, r s = 10 k, r l = 2 k, t a = 25c, ?25c t a +85c for e and f grades, 0c t a 70c for g grade, unless otherwise noted. table 2. test conditions/comments amp01e amp01f / amp01g parameter symbol min typ max min typ max unit offset voltage input offset voltage v ios t a = 25c 20 50 40 100 v t min t a t max 40 80 60 150 v input offset voltage drift tcv ios t min t a t max 1 0.15 0.3 0.3 1.0 vc output offset voltage v oos t a = 25c 1 3 2 6 mv t min t a t max 3 6 6 10 mv output offset voltage drift tcv oos r g = 1 ?55c t a +125c 20 100 50 120 v/c offset referred to input vs. positive supply psr v+ = +5 v to +15 v g = 1000 120 130 110 120 db g = 100 110 130 100 120 db g = 10 95 110 90 100 db g = 1 75 90 70 80 db t min t a t max g = 1000 120 130 110 120 db g = 100 110 130 100 120 db g = 10 95 110 90 100 db g = 1 75 90 70 80 db offset referred to input vs. negative supply psr v? = ?5 v to ?15 v g = 1000 110 125 105 115 db g = 100 95 105 90 95 db g = 10 75 85 70 75 db g = 1 55 65 50 60 db t min t a t max g = 1000 110 125 105 115 db g = 100 95 105 90 95 db g = 10 75 85 70 75 db g = 1 55 85 50 60 db input offset voltage trim range v s = 4.5 v to 18 v 2 6 6 mv output offset voltage trim range v s = 4.5 v to 18 v 2 100 100 mv input current input bias current i b t a = 25c 1 4 2 6 na t min t a t max 4 10 6 15 na input bias current drift tci b t min t a t max 40 50 pa/c input offset current i os t a = 25c 0.2 1.0 0.5 2.0 na t min t a t max 0.5 3.0 1.0 6.0 na input offset current drift tci os t min t a t max 3 5 pa/c
amp01 data sheet rev. e | page 6 of 29 test conditions/comments amp01e amp01f / amp01g parameter symbol min typ max min typ max unit input input resistance r in differential, g = 1000 1 1 g differential, g 100 10 10 g common mode, g = 1000 20 20 g input voltage range ivr t a = 25c 3 10.5 10.5 v t min t a t max 10.0 10.0 v common-mode rejection cmr v cm = 10 v, 1 k source imbalance g = 1000 125 130 115 125 db g = 100 120 130 110 125 db g = 10 100 120 95 110 db g = 1 85 100 75 90 db t min t a t max g = 1000 120 125 110 120 db g = 100 115 125 105 120 db g = 10 95 115 90 105 db g = 1 80 95 75 90 db 1 sample tested. 2 v ios and v oos nulling has minimal affect on tcv ios and tcv oos , respectively. 3 refer to the common-mode rejection section.
data sheet amp01 rev. e | page 7 of 29 v s = 15 v, r s = 10 k, r l = 2 k, t a = 25c, unless otherwise noted. table 3. amp01a / amp01e amp01b / amp01f / amp01g parameter symbol test conditions/comments min typ max min typ max unit gain gain equation accuracy g = (20 r s )/r g , accuracy measured from g = 1 to 100 0.3 0.6 0.5 0.8 % gain range g 0.1 10,000 0.1 10,000 v/v nonlinearity g = 1000 1 0.0007 0.005 0.0007 0.005 % g = 100 1 0.005 0.005 % g = 10 1 0.005 0.007 % g = 1 1 0.010 0.015 % temperature coefficient g tc 1 g 1000 1, 2 5 10 5 15 ppmc output rating output voltage swing v out r l = 2 k 13.0 13.8 13.0 13.8 v r l = 500 k 13.0 13.5 13.0 13.5 v r l = 50 k 2.5 4.0 2.5 4.0 v r l = 2 k over temperature 12.0 13.8 12.0 13.8 v r l = 500 k 3 12.0 13.5 12.0 13.5 v positive current limit output to ground short 60 100 120 60 100 120 ma negative current limit output to ground short 60 90 120 60 90 120 ma capacitive load stability 1 g 1000, no oscillations 1 0.1 1 0.1 1 f thermal shutdown temperature junction temperature 165 165 c noise voltage density, rti e n f o = 1 khz g = 1000 5 5 nv/hz g = 100 10 10 nv/hz g = 10 59 59 nv/hz g = 1 540 540 nv/hz noise current density, rti i n f o = 1 khz, g = 1000 0.15 0.15 pv/hz input noise voltage e n p-p 0.1 hz to 10 hz g = 1000 0.12 0.12 v p-p g = 100 0.16 0.16 v p-p g = 10 1.4 1.4 v p-p g = 1 13 13 v p-p input noise current i n p-p 0.1 hz to 10 hz, g = 1000 2 2 pv p-p dynamic response small-signal bandwidth (?3 db) bw g = 1 570 570 khz g = 10 100 100 khz g = 100 82 82 khz g = 1000 26 26 khz slew rate g = 10 3.5 4.5 3.0 4.5 v/s settling time to 0.01%, 20 v step g = 1 12 12 s g = 10 13 13 s g = 100 15 15 s g = 1000 50 50 s 1 guaranteed by design. 2 gain temperature coefficient does not include the effects of gain and scale resistor temperature coefficient match. 3 ?55c t a +125c for a and b grades, ?25c t a +85c for e and f grades, 0c t a 70c for g grade.
amp01 data sheet rev. e | page 8 of 29 v s = 15 v, r s = 10 k, r l = 2 k, t a = 25c, unless otherwise noted. table 4. amp01a / amp01e amp01b / amp01f / amp01g parameter symbol test conditions/comments min typ max min typ max unit sense input input resistance r in 35 50 65 35 50 65 k input current i in referenced to v? 280 280 a voltage range 1 ?10.5 +15 ?10.5 +15 v reference input input resistance r in 35 50 65 35 50 65 k input current i in referenced to v? 280 280 a voltage range 1 ?10.5 +15 ?10.5 +15 v gain to output 1 1 v/v power supply C25c t a +85c for e and f grades, C55 c t a +125c for a and b grades supply voltage range v s +v linked to +v op 4.5 18 4.5 18 v ?v linked to ?v op 4.5 18 4.5 18 v quiescent current i q +v linked to +v op 3.0 4.8 3.0 4.8 ma ?v linked to ?v op 3.4 4.8 3.4 4.8 ma 1 guaranteed by design. dice characteristics 14335-102 r g r g ?input v oos null v oos null test pin* sense reference output v? (output) v? v+ v+ (output) r s r s v ios null v ios null +input * make no electrical connection. figure 2. die size 0.111 in 0.149 in, 16,539 sq. mils (2.82 mm 3.78 mm, 10.67 sq. mm)
data sheet amp01 rev. e | page 9 of 29 wafer test limits ( amp01nbc ) v s = 15 v, r s = 10 k, r l = 2 k, t a = 25c, unless otherwise noted. electrical tests are performed at wafer probe to the limits shown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. consult the factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. table 5. parameter symbol test conditions/comments min typ max unit offset voltage input offset voltage v ios 60 v input offset voltage drift tcv ios 0.15 v/c output offset voltage v oos 4 mv output offset voltage drift tcv oos r g = 20 v/c offset referred to input vs. positive supply psr v+ = 5 v to 15 v g = 1000 120 db g = 100 110 db g = 10 95 db g = 1 75 db offset referred to input vs. negative supply psr vC = C5 v to C15 v g = 1000 105 db g = 100 90 db g = 10 70 db g = 1 50 db input current input bias current i b 4 na input bias current drift tci b 40 pa/c input offset current i os 1 na input offset current drift tci os 3 pa/c input input voltage range ivr guaranteed by cmr tests 10 v min common-mode rejection cmr v cm = 10 v g = 1000 125 db g = 100 120 db g = 10 100 db g = 1 85 db gain gain equation accuracy g = (20 r s )/r g 0.6 % output rating output voltage swing v out r l = 2 k ?13 +13 v r l = 500 k ?13 +13 v r l = 50 k ?2.5 +2.5 v output current limit output to ground short ?60 +60 ma output to ground short ?120 +120 ma quiescent current i q +v linked to +v op 4.8 ma ?v linked to ?v op 4.8 ma noise nonlinearity e n g = 1000 0.0007 % voltage noise density i n g = 1000, f o = 1 khz 5 nv/hz current noise density e n p-p g = 1000, f o = 1 khz 0.15 pa/hz voltage noise i n p-p g = 1000, 0.1 hz to 10 hz 0.12 v p-p current noise bw g = 1000, 0.1 hz to 10 hz 2 pa p-p dynamic response small-signal bandwidth (?3 db) sr g = 1000 26 khz slew rate t s g = 10 4.5 v/s settling time to 0.01%, 20 v step, g = 1000 50 s
amp01 data sheet rev. e | page 10 of 29 absolute maximum ratings table 6. parameter rating supply voltage 18 v internal power dissipation 1 500 mw common-mode input voltage supply voltage differential input voltage r g 2 k 20 v 10 v i ndefinite ?65c to +150c r g 2 k output short-circuit d u ration stor ag e temperature range operating temperatur e range amp01a , amp01b ?55c to +125c amp01e , amp01f ?25c to +85c lead temperature (soldering, 60 sec) 300c dice junction temperature (t j ) ?65c to +150c 1 see table 7 for maximum ambient temper ature rating and derating factor stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 7. thermal resistance package type ja jc unit q-18 (100c max ambient) 70.4 10.2 mw/c rw-20 73.7 23.9 mw/c esd caution
data sheet amp01 rev. e | page 11 of 29 pin configurations and function descriptions ?v op v? +in v ios null v ios null v+ +v op r s r s output reference r g r g ?in v oos null v oos null sense test pin* *make no electrical connection. 1 2 3 4 18 17 16 15 5 14 6 13 7 12 8 11 9 10 a mp01 top view (not to scale) 14335-001 figure 3. 18-lead cerdip table 8. 18-lead cerdip pin function descriptions pin no. mnemonic description 1 r g gain resistor pin. install a resistor between 200 k and 100 to pin 2. 2 r g gain resistor pin. install a resistor between 200 k and 100 to pin 1. 3 ?in inverting signal input. 4 v oos null output offset voltage null. connect a 100 k trimmer across pin 4 and pin 5 with wiper to negative supply voltage. 5 v oos null output offset voltage null. connect a 100 k trimmer across pin 4 and pin 5 with wiper to negative supply voltage. 6 test pin test pin. pin 6 is reserved for factory test. do not connect. 7 sense this pin completes the feedback loop for the inve rting input amplifier. normal ly connected to the output. 8 reference this pin shifts the output cmv. normally connected to ground. 9 output output of the in-amp. 10 ?v op negative supply voltage for output amplifier. 11 v? negative supply voltage for input amplifiers. 12 v+ positive supply voltage for input amplifiers. 13 +v op positive supply voltage for output amplifier. 14 r s scale resistor. see the gain section and figure 32 for value. 15 r s scale resistor. see the gain section and figure 32 for value. 16 v ios null input offset voltage null. connect a 100 k trimmer across pin 16 and pin 17 with wiper to negative supply voltage. 17 v ios null input offset voltage null. connect a 100 k trimmer across pin 16 and pin 17 with wiper to negative supply voltage. 18 +in noninverting signal input.
amp01 data sheet rev. e | page 12 of 29 *make no electrical connection ?v op output reference test pin* ?in v oos null sense test pin* v oos null r g v? v+ +v op test pin* +in r s r s r g v ios null v ios null amp01 top view (not to scale) 1 2 3 4 20 19 18 17 5 16 6 15 7 14 8 13 9 12 10 11 14335-003 figure 4. 20-lead soic table 9. 20-lead soic pin function descriptions pin no. mnemonic description 1 r g gain resistor pin. install a resistor between 200 k and 100 to pin 20. 2 test pin test pin. pin 2 is reserved for factory test. do not connect. 3 ?in inverting signal input 4 v oos null output offset voltage null. connect a 100 k trimmer across pin 4 and pin 5 with wiper to negative supply voltage. 5 v oos null output offset voltage null. connect a 100 k trimmer across pin 4 and pin 5 with wiper to negative supply voltage. 6 test pin test pin. pin 6 is reserved for factory test. do not connect. 7 sense this pin completes the feedback loop for the inve rting input amplifier. normal ly connected to the output. 8 reference this pin shifts the output cmv. normally connected to ground. 9 output output of the in-amp. 10 ?v op negative supply voltage for output amplifier. 11 v? negative supply voltage for input amplifiers. 12 v+ positive supply voltage for input amplifiers. 13 + v op positive supply voltage for output amplifier. 14 r s scale resistor. see the gain section and figure 32 for value. 15 r s scale resistor. see the gain section and figure 32 for value. 16 v ios null input offset voltage null. connect a 100 k trimmer across pin 16 and pin 17 with wiper to negative supply voltage. 17 v ios null input offset voltage null. connect a 100 k trimmer across pin 16 and pin 17 with wiper to negative supply voltage. 18 +in noninverting signal input. 19 test pin test pin. pin 19 is reserved for factory test. do not connect. 20 r g gain resistor pin. install a resistor between 200 k and 100 to pin 1.
data sheet amp01 rev. e | page 13 of 29 typical performance characteristics temperature (c) 150 ?50?75 ?25 0 25 75 100 125 50 input offset voltage (v) 50 40 ?40 0 ?10 ?20 ?30 30 10 20 v s = 15v 14335-005 figure 5. input offset voltage vs. temperature power supply voltage (v) input offset voltage (v) 8 6 ?6 0 5 2 0 10 15 2 0 ?2 ?4 4 t a = +25c unit no. 1 2 3 4 14335-006 figure 6. input offset voltage vs. supply voltage 150 ?50 ?75 ?25 0 25 75 100 125 50 temperature (c) output offset voltage (mv) 5 4 ?4 0 ?1 ?2 ?3 3 1 2 ?5 v s = 15v 14335-007 figure 7. output offset voltage vs. temperature power supply voltage (v) output offset voltage change (mv) 2.5 2.0 ?1.0 0 5 2 5 10 15 20 1.0 0.5 0 ?0.5 1.5 t a = +25c 14335-008 figure 8. output offset volt age change vs. supply voltage temperature (c) 150 ?50?75 ?25 0 25 75 100 125 50 input bias current (na) 5 ?2 4 2 1 0 ?1 3 v s = 15v 14335-009 figure 9. input bias current vs. temperature power supply voltage (v) input bias current (na) 2.0 1.5 ?1.5 0 0.5 0 ?0.5 ?1.0 1.0 t a = +25c 14335-010 5 10 15 20 figure 10. input bias current vs. supply voltage
amp01 data sheet rev. e | page 14 of 29 150 ?50?75 ?25 0 25 75 100 125 50 temperature (c) input offset current (na) 0.8 ?0.6 0.6 0.2 0 ?0.2 ?0.4 0.4 v s = 15v 14335-011 figure 11. input offset current vs. temperature voltage gain (g) common-mode rejection (db) 140 100 10k 1 120 1k 100 10 130 110 v s = 15v t a = +25c 14335-012 figure 12. common-mode rejection vs. voltage gain 100k 10k 11k 100 10 frequency (hz) common-mode rejection (db) 140 0 120 100 80 60 40 20 g = 1000 g = 100 g = 1 g = 10 v cm = 2v p-p v s =15v t a = +25c 14335-013 figure 13. common-mode rejection vs. frequency v s = 15v v s = 10v v s = 5v 150 ?50?75 ?25 0 25 75 100 125 50 temperature (c) common-mode input v o ltage (v) 16 0 14 8 6 4 2 12 10 v dm = 0 14335-014 figure 14. common-mode voltage range vs. temperature 100k 10k 11k 100 10 frequency (hz) power supply rejection (db) 140 0 120 100 80 60 40 20 g = 1000 g = 100 g = 10 g = 1 v s =15v t a = +25c ? v s =1v 14335-015 figure 15. positive power supply rejection (psr) vs. frequency 100k 10k 11k 100 10 frequency (hz) power supply rejection (db) 140 0 120 100 80 60 40 20 g = 1000 g = 100 g = 10 g = 1 v s = 15v t a = +25c ? v s =1v 14335-016 figure 16. negative psr vs. frequency
data sheet amp01 rev. e | page 15 of 29 10k 1k 100 10 load resistance ( ? ) ouitput voltage (v) 18 10 14 16 12 8 6 4 2 0 v s = 15v 14335-017 figure 17. maximum output voltage vs. load resistance 100k 1m 10k 1k 100 frequency (hz) peak-to-peak amplitude (v) 30 10 20 25 15 r l = 2k ? 5 0 v s = 15v 14335-018 figure 18. maximum output swing vs. frequency 100k 10k 1m 1k 100 10 frequency (hz) output impedance ( ? ) 100 10 1.0 0.1 0.01 0.001 g = 1000 g = 1 v s = 15v i out = 20ma p-p 14335-019 figure 19. closed-loop outp ut impedance vs. frequency 100k 10k 1m 1k 100 110 frequency (hz) voltage gain (db) 80 0 40 60 20 ?20 ?40 g = 1000 g = 100 g = 10 g = 1 v s = 15v t a = +25c 14335-020 figure 20. closed-loop voltage gain vs. frequency 10k 1k 100 10 frequency (hz) total harmonic distortion (%) 0.08 0.04 0.06 0.07 0.05 0.03 0.02 0.01 0 g = 1000 g = 100 g = 10 g = 1 v s = 15v r l = 600 ? v out = 20v p-p 14335-021 figure 21. total harmonic distortion vs. frequency 1k 100 load resistance ( ? ) total harmonic di s tortion (%) 0.02 0.01 10k 0 v s = 15v g = 100 f = 1khz v out = 20v p-p 14335-022 figure 22. total harmonic distortion vs. load resistance
amp01 data sheet rev. e | page 16 of 29 100 10 11k voltage gain (g) slew r a te (v/s) 6 3 4 5 2 1 0 v s = 15v 14335-023 figure 23. slew rate vs. voltage gain load capacitance (f) slew r a te (v/s) 6 2 1 100p 4 100n 1n 10n 5 3 1 0 v s = 15v 14335-024 figure 24. slew rate vs. load capacitance voltage gain (g) settling time (s) 70 40 1k 50 100 10 1 60 30 20 10 v s = 15v 20v step 14335-025 figure 25. settling time to 0.01% vs. voltage gain frequency (hz) voltage noise (nv/ hz) 15 5 10k 1 10 1k 10 100 0 g = 1000 14335-026 figure 26. voltage noise density vs. frequency voltage gain (g) 1k 1 10 100 voltage noise (nv/ 14335-027 figure 27. rti voltage noise density vs. gain power supply voltage (v) positive supply current (ma) 8 7 0 0 5 2 0 10 15 4 3 2 1 6 5 t a = +25c 14335-028 figure 28. positive supply current vs. supply voltage
data sheet amp01 rev. e | page 17 of 29 power supply voltage (v) neg a tive supply current (ma) ? 8 ?7 0 0 5 2 0 10 15 ?4 ?3 ?2 ?1 ?6 ?5 t a = +25c 14335-029 figure 29. negative supply current vs. supply voltage 150 ?50?75 ?25 0 25 75 100 125 50 temperature (c) positive supply current (ma) 6 0 5 4 3 2 1 v s = 15v 14335-030 figure 30. positive supply current vs. temperature 150 ?50?75 ?25 0 25 75 100 125 50 temperature (c) ne g a tive supply current (ma) ? 6 0 ?5 ?4 ?3 ?2 ?1 v s = 15v v sense = v ref = 0v 14335-031 figure 31. negative supply current vs. temperature
amp01 data sheet rev. e | page 18 of 29 theory of operation input and output offset voltages instrumentation amplifiers have independent offset voltages associated with the input and output stages. still, temperature variations cause offset shifts regardless of initial zero adjustments. systems with auto-zero correct for offset errors, rendering initial adjustment unnecessary. however, many high gain applications do not have auto-zero. for such applications, both offsets can be nulled, which has minimal effect on tcv ios and tcv oos . the input offset component is directly multiplied by the amplifier gain, whereas output offset is independent of gain. therefore, at low gain, output offset errors dominate, whereas at high gain, input offset errors dominate. the overall offset voltage, v os , referred to the output (rto) is calculated as follows: v os ( rto) = (v ios g ) + v oos (1) where: v ios is the input offset voltage specification. v oos is the output offset voltage specification. g is the amplifier gain. input offset nulling alone is recommended with amplifiers having fixed gain above 50. output offset nulling alone is recommended when gain is fixed at 50 or below. in applications requiring both initial offsets to be nulled, the input offset is nulled first by short circuiting r g , then the output offset is nulled with the short removed. the overall offset voltage drift, tcv os , referred to the output is a combination of input and output drift specifications. input offset voltage drift is multiplied by the amplifier gain, g, and summed with the output offset drift: tcv os ( rto) = (tcv ios g ) + tcv oos (2) where: tcv ios is the input offset voltage drift. tcv oos is the output offset voltage specification. frequently, the amplifier drift is referred back to the input (rti), which is then equivalent to an input signal change: g tcv tcvrtitcv oos ios os ? ) ( (3) for example, the maximum input referred drift of an amp01ex set to g = 1000 becomes, maxc/v4.0 1000 c/v100 c/v3.0)( ??? ?? ???? rtitcv os input bias and offset currents input transistor bias currents are additional error sources that can degrade the input signal. bias currents flowing through the signal source resistance appear as an additional offset voltage. equal source resistance on both inputs of an instrumentation amplifier (ia) minimizes offset changes due to bias current variations with signal voltage and temperature. however, the difference between the two bias currents, the input offset current, produces a nontrimmable error. the magnitude of the error is the offset current times the source resistance. a current path must always be provided between the differential inputs and analog ground to ensure correct amplifier operation. floating inputs, such as thermocouples, must be grounded close to the signal source for best common-mode rejection. gain the amp01 uses two external resistors for setting voltage gain over the range of 0.1 to 10,000. the magnitudes of the scale resistor, r s , and the gain set resistor, r g , are related by the formula g = 20 r s /r g , where g is the selected voltage gain (see figure 32). reference output v + v? r s r g +in ?in v oltage gain, g = 20 r s r g sense amp01 14 15 13 12 7 9 8 11 10 3 2 1 18 14335-032 figure 32. basic amp01 connections for gains of 0.1 to 10,000 the magnitude of r s affects linearity and output referred errors. circuit performance is characterized using r s = 10 k when operating on 15 v supplies and driving a 10 v output. r s can be reduced to 5 k in many applications, particularly when operating on 5 v supplies, or if the output voltage swing is limited to 5 v. bandwidth is improved with r s = 5 k, increasing the common-mode rejection by approximately 6 db at low gain. reducing the value below 5 k can cause instability in some circuit configurations and usually has no advantage. high voltage gains between 2 and 10,000 require very low values of r g . for r s = 10 k and a v = 2000, r g = 100 ; this value is the practical lower limit for r g . below 100 , mismatch of wire bond and resistor temperature coefficients (tcs) introduce significant gain tc errors. therefore, for gains above 2000, r g must be kept constant at 100 and r s increased. the maximum gain of 10,000 is obtained with r s set to 50 k.
data sheet amp01 rev. e | page 19 of 29 metal film or wire wound resistors are recommended for best results. the absolute values and tcs are not too important, only the ratiometric parameters. ac amplifiers require good gain stability with temperature and time, but dc performance is unimportant. therefore, low cost metal film types with tcs of 50 ppm/c are usually adequate for r s and r g . realizing the full potential of the offset voltage and gain stability of the amp01 requires precision metal film or wire wound resistors. achieving a 15 ppm/c gain tc at all gains requires r s and r g temperature coefficient matching to 5 ppm/c or better. voltage gain 1m 10k 1 resistance ( ? ) 10k 10 100 1k v s = 15v 100k 1k 100 r s r g 14335-033 figure 33. r g and r s selection gain accuracy is determined by the ratio accuracy of r s and r g combined with the gain equation error of the amp01 (0.6% maximum for a and e grades). all instrumentation amplifiers require attention to layout so that thermocouple effects are minimized. thermocouples formed between copper and dissimilar metals can destroy the tcv os performance of the amp01 , which is typically 0.15 v/c. resistors themselves can generate thermoelectric emfs when mounted parallel to a thermal gradient. vishay resistors are recommended because a maximum value for thermoelectric generation is specified. however, where thermal gradients are low and gain tcs of 20 ppm to 50 ppm are sufficient, general- purpose metal film resistors can be used for r g and r s . common-mode rejection ideally, an instrumentation amplifier responds only to the difference between the two input signals and rejects common- mode voltages and noise. in practice, there is a small change in output voltage when both inputs experience the same common- mode voltage change; the ratio of these voltages is called the common-mode gain. common-mode rejection (cmr) is the logarithm of the ratio of differential-mode gain to common- mode gain, expressed in db. cmr specifications are normally measured with a full-range input voltage change and a specified source resistance unbalance. the current feedback design used in the amp01 inherently yields high common-mode rejection. unlike resistive feedback designs, typified by the 3-op-amp ia, the cmr is not degraded by small resistances in series with the reference input. a slight but trimmable output offset voltage change results from resistance in series with the reference input. the common-mode input voltage range (cmvr) for linear operation can be calculated from the formula, r g v ivr cmvr out 2 || (4) where: ivr is the data sheet specification for the input voltage range. v out is the maximum output signal. g is the chosen voltage gain. for example, at 25c, ivr is specified as 10.5 v minimum with 15 v supplies. using a 10 v maximum swing output and substituting the figures in equation 4 simplifies the formula to r g cmvr 5 5.10 (5) for all gains greater than or equal to 10, cmvr is 10 v minimum; at gains below 10, cmvr is reduced. active guard drive rejection of common-mode noise and line pickup can be improved by using shielded cable between the signal source and the ia. shielding reduces pickup, but increases input capacitance, which in turn degrades the settling-time for signal changes. furthermore, any imbalance in the source resistance between the inverting and noninverting inputs, when capacitively loaded, converts the common-mode voltage into a differential voltage. this effect reduces the benefits of shielding. ac common-mode rejection is improved by bootstrapping the input cable capacitance to the input signal, a technique called guard driving. this technique effectively reduces the input capacitance. a single guard-driving signal is adequate at gains above 100 and must be the average value of the two inputs. the value of the external gain resistor, r g , is split between two resistors, r g1 and r g2 ; the center tap provides the required signal to drive the buffer amplifier (see figure 34). grounding the majority of instruments and data acquisition systems have separate grounds for analog and digital signals. analog ground can also be divided into two or more grounds that are tied together at one point, usually the analog power-supply ground. in addition, the digital and analog grounds can be joined, normally at the analog ground pin on the analog-to-digital converter (adc). following this basic grounding practice is essential for good circuit performance (see figure 35). mixing grounds causes interactions between digital circuits and the analog signals. because the ground returns have finite resistance and inductance, hundreds of millivolts can be developed between the system ground and the data acquisition components. using separate ground returns minimizes the current flow in the sensitive analog return path to the system
amp01 data sheet rev. e | page 20 of 29 ground point. consequently, noisy ground currents from logic gates do not interact with the analog signals. inevitably, two or more circuits are joined together with their grounds at differential potentials. in these situations, the differential input of an instrumentation amplifier, with its high cmr, can accurately transfer analog information from one circuit to another. sense and reference terminals the sense terminal completes the feedback path for the instrumentation amplifier output stage and is normally connected directly to the output. the output signal is specified with respect to the reference terminal, which is normally connected to analog ground. voltage gain, g = 20 r s r g1 a v = 500 with components shown * +15v c1 0.047f + c5 10f r5 * * sense output * solder link reference * ground r3 c4 0.047f + c6 10f c2 0.047f vr1 100k ? vr2 100k ? r g1 400 ? +in ?in r g3 200 ? r g2 200 ? 741 +15v ?15v guard drive r2 1m ? r1 1m ? signal ground r s 10k ? c3 0.047f ?15v r4 r s nc * amp01 r s v ios null v oos null v+ v? r g r g 15 14 6 13 12 7 18 1 2 3 16 17 4 5 10 11 8 9 7 6 4 3 2 14335-034 figure 34. amp01 evaluation circuit showing guard-drive connection hold capacitor c = 0.047f ceramic capacitors digital data output analog ground digital ground adc cc 7 8 9 output reference smp-11 sample and hold c + 4.7f digital ground cc v5+ v0 digital power supply ?15v +15v 0v analog power supply cc amp01 14335-035 figure 35. basic grounding practice
data sheet amp01 rev. e | page 21 of 29 if heavy output currents are expected and the load is situated some distance from the amplifier, voltage drops due to track or wire resistance cause errors. voltage drops are particularly troublesome when driving 50 loads. under these conditions, the sense and reference terminals can be used to remote sense the load, as shown in figure 36. this method of connection puts the i r drops inside the feedback loop and virtually eliminates the error. an unbalance in the lead resistances from the sense and reference pins does not degrade cmr, but does change the output offset voltage. for example, a large unbalance of 3 changes the output offset by only 1 mv. driving 50 loads output currents of 50 ma are guaranteed into loads of up to 50 and 26 ma into 500 . in addition, the output is stable and free from oscillation even with a high load capacitance. the combination of these unique features in an instrumentation amplifier allows low level transducer signals to be conditioned and directly transmitted through long cables in voltage or current form. increased output current brings increased internal dissipation, especially with 50 loads. for this reason, the power-supply connections are split into two pairs; pin 10 and pin 13 connect to the output stage only, and pin 11 and pin 12 provide power to the input and following stages. dual supply pins allow dropper resistors to be connected in series with the output stage so excess power is dissipated outside the package. additional decoupling is necessary between pin 10 and pin 13 to ground to maintain stability when dropper resistors are used. figure 37 shows a complete circuit for driving 50 loads. amp01 +in ? in r g 18 1 2 3 14 15 12 13 7 9 8 10 11 v? v + sense reference * * output ground twisted pairs remote load in4148 diodes are optional. diodes limit the output voltage excursion if sense and/or reference lines become disconnected from the load. * r s 14335-036 figure 36. remote load sensing +in ?in r g amp01 14 15 12 13 7 9 8 10 11 18 1 2 3 r s 5k ? r1 130 ? 1w c1 0.047f 0.047f +15v sense reference v out 3v max 50 ? load c2 0.047f r2 130 ? 1w 0.047f ?15v power bandwidth, g = 100, 130khz power bandwidth, g = 10, 200khz thd: ~0.04% at 1khz, 2v rms voltage gain, g = 20 r s r g r1 and r2 resistors reduce ic dissipation 14335-037 figure 37. driving 50 loads
amp01 data sheet rev. e | page 22 of 29 heatsinking to maintain high reliability, the die temperature of any ic must be kept as low as practicable, preferably below 100c. although most amp01 application circuits produce very little internal heatlittle more than the quiescent dissipation of 90 mw some circuits raise that to several hundred milliwatts (for example, the 4 ma to 20 ma current transmitter application; see figure 40). excessive dissipation causes thermal shutdown of the output stage, thus protecting the device from damage. a heatsink is recommended in power applications to reduce the die temperature. several appropriate heatsinks are available; the thermalloy 6010b is especially easy to use and is inexpensive. intended for dual-in-line packages, the heatsink can be attached with a cyanoacrylate adhesive. this heatsink reduces the thermal resistance between the junction and ambient environment to approximately 80c/w. junction (die) temperature can then be calculated by using the following relationship: ja a j d tt p ? ? where: p d is the internal dissipation of the device. t j is the junction temperature. t a is the ambient temperature. ja is the thermal resistance from junction to ambient. overvoltage protection instrumentation amplifiers invariably sit at the front end of instrumentation systems where there is a high probability of exposure to overloads. voltage transients, failure of a transducer, or removal of the amplifier power supply while the signal source is connected can destroy or degrade the performance of an unprotected amplifier. although it is impractical to protect an ic internally against connection to power lines, it is relatively easy to provide protection against typical system overloads. the amp01 is internally protected against overloads for gains of up to 100. at higher gains, the protection is reduced and some external measures may be required. limited internal overload protection is used so that noise performance is not significantly degraded. amp01 noise level approaches the theoretical noise floor of the input stage, which is 4 nv/hz at 1 khz when the gain is set at 1000. noise is the result of shot noise in the input devices and johnson noise in the resistors. resistor noise is calculated from the values of r g (200 at a gain of 1000) and the input protection resistors (250 ). active loads for the input transistors contribute less than 1 nv/hz of noise. the measured noise level is typically 5 nv/hz. diodes across the input transistors base-emitter junctions, combined with 250 input resistors and r g , protect against differential inputs of up to 20 v for gains of up to 100. the diodes also prevent avalanche breakdown that degrade the i b and i os specifications. decreasing the value of r g for gains above 100 limits the maximum input overload protection to 10 v. external series resistors can be added to guard against higher voltage levels at the input, but resistors alone increase the input noise and degrade the signal-to-noise ratio, especially at high gains. protection can also be achieved by connecting back to back 9.1 v zener diodes across the differential inputs. this technique does not affect the input noise level and can be used down to a gain of 2 with minimal increase in input current. although voltage-clamping elements look like short circuits at the limiting voltage, the majority of signal sources provide less than 50 ma, producing power levels that are easily handled by low power zener diodes. simultaneous connection of the differential inputs to a low impedance signal above 10 v during normal circuit operation is unlikely. however, additional pr otection involves adding 100 current-limiting resistors in each signal path prior to the voltage clamp, the resistors increase the input noise level to just 5.4 nv/hz (refer to figure 38). input components, whether multiplexers or resistors, should be carefully selected to prevent the formation of thermocouple junctions that would degrade the input signal. v out +15v +in ?in amp01 9.1v 1w zeners 100 1w * 100 1w * resistors, see text. * optional protection linear input range, 5v maximum differential protection to 30v ?15v 14335-038 figure 38. input overvoltage protection for gains of 2 to 10,000 power supply considerations achieving the rated performance of precision amplifiers in a practical circuit requires careful attention to external influences. for example, supply noise and changes in the nominal voltage directly affect the input offset voltage. a psr of 80 db means that a change of 100 mv on the supply produces a 10 v input offset change. consequently, care must be taken in choosing a power source with low output noise, good line and load regulation, and good temperature stability.
data sheet amp01 rev. e | page 23 of 29 applications circuits i out r1 100 ? r2 200 ? r out trim sense 7 9 8 reference 10 11 15 14 12 13 18 1 2 3 r g 2k ? +in ? in v in r s 2k ? ?15v 0.047f 0.047f +15v compliance, typically 10v linearity ~0.01% output resistance at 20ma ~5m ? power bandwidth (?3db) ~60khz into 500 ? load i out = v in 20 r s r g r1 amp01 r1 = 100 ? for i out = 20ma v in = 100mv for 20ma full scale r g r g r s r s v+ v? 14335-039 figure 39. high compliance bipolar current source with 13-bit linearity r out trim 7 9 8 10 11 15 14 12 13 18 1 2 3 r g 2.75k ? + in ? in 0v r s 2k? 0.047f amp01 compliance of i out , +20v with +30v supply (output with regards to 0v) differential input of 100mv for 16ma span output resistance ~5m ? at i out = 20ma linearity 0.01% of span 0.047f r5 2.21k ? r6 500 ? zero trim r2 200 ? ref-02 r3 100 ? 4 6 2 r1 100 ? +15v to +30v i out 4ma to 20ma ?5v all resistors 1% metal film r s r s r g r g v? v+ r4 100 ? 14335-040 figure 40. 13-bit linear 4 ma to 20 ma transmi tter constructed by adding a voltage reference; thermocouple signals can be accepted without preamplification
amp01 data sheet rev. e | page 24 of 29 + +in ?in r g 14 15 12 13 7 9 8 10 11 18 1 2 3 10k ? sense reference 0.047f voltage gain, g = 100 power bandwidth (?3db), 60khz quiescent current, 4ma linearity ~0.01% at full output into 10 ? 10f 0.047f 100 ? 0.047f 2n4921 2n4918 +15 v v out (10v into 10 ? ) ?15v amp01 r s r s v+ v? r g r g gnd 14335-041 10uf figure 41. adding two transistors increa ses output current to 1 a without aff ecting the quiescent current of 4 ma; power bandwidth is 60 khz 0.047f out 100k ? 100k ? +in ?in ic2 +15v ?15v 7 6 4 3 2 r s 10k ? r s amp01 r s v ios null v oos null v+ v? r g r g 15 14 13 12 7 18 1 2 3 16 17 4 5 10 11 8 9 sense reference gnd 0.047f ?15v + + + + 10 8 6 4 3 ic1 +15v g1 g10 g100 g1000 57911 ttl-compatible inputs 27k ? 2.7k ? 12 13 14 12 47k ? 47k ? 47k ? 47k ? 200k ? 20k ? 2k ? 196 ? q4 q5 q3 q2 q1 +15 v q1, q2...........j110 q3, q4, q5....j107 ic1 ...............cmp-04 ic2 ...............op15gz linearity ~0.005%, g = 10 and 100 ~0.02%, g = 1 and 1000 gain accuracy, untrimmed ~0.5% settling time to 0.01%, all gains, less than 75s gain switching time, less than 100s 14335-042 figure 42. amp01 makes an excellent programmable-gain instrumentation amplifier; combined gain-switching and settling time to 13 bits falls below 100 s; linearity is better than 12 bits over a gain range of 1 to 1000
data sheet amp01 rev. e | page 25 of 29 15 14 18 1 2 3 r g ?in r s 10k ? maximum output, 20v p-p into 600 ? thd: 0.01% at 1khz, 20v p-p into 600 ? , g = 10 20 r s r g voltage gain, g = amp01 r g r g r s r s + r l differential output output common-mode reference (5v max) op37 2 3 7 6 4 470pf 1.5k ? *5k ? *5k ? * matched to 0.1% 7 8 9 13 10 12 11 0v v+ v? ?15v +15v 0v 0.047f 0.047f 0v sense +in reference 14335-043 figure 43. a differential input instrumentation amplifier with differential output replaces a transformer in many applications; output drives a 600 load at low distortion (0.01%) 18 1 2 3 r1 390 ? closed-loop voltage gain must be greater than 50 for stable operation r2 r3 1 + voltage gain, g = v in amp01 r g r g r s r s 7 8 9 13 10 12 11 v+ v? v out +15v nc nc ?15v 0.047f + 10f r2 4.95k ? r3 50 ? r l c l 15 14 power bandwidth (?3db) ~ 150khz total harmonic distortion ~ 0.006% at 1khz, 20v p-p into 500 ? // 1000pf 0.047f + 10f ref sense nc = no connect 14335-044 figure 44. configuring the amp01 as a noninverting operational amplifie r provides exceptional performance; output handles low load impedances at very low distortion (0.006%)
amp01 data sheet rev. e | page 26 of 29 18 1 2 3 r4 v in 7 8 9 10 11 v out r1 = r2 gain (g) r3 = r1 // r2 r4 = 1.5k ? at g = 1 1.2k ? at g = 10 120? at g = 100 and 1000 ?15v + 10f 15 14 20v p-p into 500 ? // 1000pf. total harmonic distortion: <0.005% at 1khz, v out = 20v p-p nc nc r2 220k ? 0.01f 4.7k ? r3 +15v amp01 r g r g r s r s sense v? ref 0.047f 0.047f 10f + g = 1 to 1000 nc = no connect r1 12 13 v+ 14335-045 figure 45. inverting operational amplifier configuration has excellent linearity over the gain range 1 to 1000, typically 0.005 %; offset voltage drift at unity gain is improved over the drift in the instrumentation amplifier configuration 18 1 2 3 r g 3k ? v in amp01 r g r g ref sense 7 8 9 13 10 12 11 v+ v? v out +15v nc nc ?15v 0.047f + 10f r2 4.7k ? r l c l 15 14 power bandwidth (?3db) ~ 60khz total harmonic distortion ~ 0.001% at 1khz, 20v p-p into 500 ? // 1000pf nc = no connect 0.047f + 10f 680pf 0.01f r3 330 ? r1 4.7k ? r s r s 14335-046 figure 46. stability with large capacitive loads comb ined with high output current capability make the amp01 ideal for line driving applications; offset voltage drift approaches the tcv ios limit (0.3 v/c)
data sheet amp01 rev. e | page 27 of 29 18 1 2 3 9 13 10 12 11 v? 200k ? 20k ? 2k ? 200 ? g 1 g 10 g 100 g 1000 v + r g r g 7 8 1/2 op215 + ? 8 4 v? v+ 1 2 3 1.82k ? 1f 16.2k ? output 1/2 op215 + ? 1.62m ? 9.09k ? g 1000 g 1,10,100 100 ? 1k ? 8 amp01 14 15 10k ? r s r s r g r g 16.2k ? 1f e n (g = 1, 10, 100) = e out 1000 g e n (g = 1000) = e out 100 g 1f 5 6 7 14335-047 figure 47. noise test circuit (0.1 hz to 10 hz) 18 1 2 3 9 13 10 12 11 200k ? 0.1% 20k ? 0.1% 2k ? 0.1% 200 ? 0.1% g 1 g 10 g 100 g 1000 r g r g 7 8 8 14 15 0.047f 47f 0.0 v+ v? 10k ? 0.1% 10 ? 0.1% 102 ? 0.1% 1.1k ? 0.1% g 1000 g 100 g 1 g 10 10k ? 0.1% 2k ? 0.1% r g r g amp01 r s r s 1.91k ? 0.1% 200 ? 10t 2 hsch-1001 v in 20v p-p v out 14335-048 figure 48. settling time test circuit
amp01 data sheet rev. e | page 28 of 29 0.047f v out r s 10k ? 15 14 13 12 7 18 1 2 3 10 11 8 9 sense reference r s amp01 r s v+ v? r g r g r g 200 ? dg390 analog switch 1 3 6 8 +in ?in 16 9 10 15 4 5 14 13 13 4 1, 2 16 3 0.01f r1 100 ? 15k ? 1ma 7.5k ? 14 7.5k ? ttl input "offset" 0v ?15v ttl input "zero" +15 v voltage gain, g = 20 r s r g 15 dac-08 11 0.047f 14335-049 figure 49. instrumentation amplifier with auto-zero +18 v ?18v 10k ? sense amp01 14 15 13 12 7 9 8 11 10 3 2 1 18 0.047f v out 10k ? 0.047f r s r s r g r g 14335-050 figure 50. burn-in circuit
data sheet amp01 rev. e | page 29 of 29 outline dimensions controlling dimensions are in inches; millimeters dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 18 19 10 0.310 (7.87) 0.220 (5.59) 0.005 (0.13) min 0.098 (2.49) max 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 0.960 (24.38) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 15 0 pin 1 figure 51. 18-lead ceramic dual in-line package [cerdip] (q-18) dimensions shown in inches and (millimeters) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-ac 13.00 (0.5118) 12.60 (0.4961) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 20 11 10 1 1.27 (0.0500) bsc 06-07-2006-a figure 52. 20-lead standard small outline package [soic_w] wide body (rw-20) dimensions shown in millimeters and (inches) ordering guide model 1 temperature range package description package option amp01ax C55c to +125c 18-lead ceramic dual in-line package [cerdip] q-18 amp01bx C55c to +125c 18-lead ceramic dual in-line package [cerdip] q-18 amp01ex ?25c to +85c 18-lead ceramic dual in-line package [cerdip] q-18 amp01fx ?25c to +85c 18-lead ceramic dual in-line package [cerdip] q-18 amp01gsz 0c to 70c 20-lead standard small outline package [soic_w], 13 tape and reel rw-20 AMP01GSZ-REEL 0c to 70c 20-lead standard small outline package [soic_w], 13 tape and reel rw-20 amp01nbc die 1 standard military drawing available for the 5962-8863001va, 5962-88630023a, and 5962-8863002va. ?1999C2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d14335-0-1/17(e)

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